Computer Architecture and Design

CARD: Course Information

mcorey — Fri, 28 Jul 2023 16:14:27 +0000

CARD: Course Information mcorey Fri, 28/07/2023 - 17:14

Course Outline

The aim of this course is to give you a comparatively deep understanding of computer architecture, to an intermediate level, together with a solid understanding of techniques used to design the logical building blocks from which a computer is constructed. We consider an intermediate level in computer architecture to extend up to the point where you will have a good understanding of instruction set architecture, single-issue in-order pipelined execution of instructions, superscalar out-of-order execution, and the memory hierarchies required by those processors. Within a processor, we explore the principles and practice of arithmetic and logic unit design, of the caches from which memory hierarchies are constructed, and the memory and logic gate technologies from which computers are constructed. Throughout the course, there is a strong emphasis on the Quantitative Approach to computer architecture; this informs not only the theoretical topics but also the practical assignments, which always embody some element of the quantitative approach.

The philosophy of this course is that learning about computer architecture is particularly effective if reinforced by implementing key aspects of processor design, in real hardware when feasible, but also at higher levels of abstraction using simulated systems. This approach has been used very effectively in the previous Computer Design and Computer Architecture courses, and feedback often cites the value placed on the lab exercises by students.

Outline Contents

Fundamentals
Review of logic design and implementation technologies; from simple combinational logic to state machines for sequential circuits; logic design using Verilog and introduction to FPGAs.
Register Transfer Level design principles; registers, clocks, timing budgets, setup and hold margins, clock skew, clock-domain crossing and synchronization, metastability.
Quantitative computer architecture; performance evaluation methods and metrics, principles of high-performance design.

Processor Architecture
Instruction Set Architecture (ISA) design; instruction set classes, registers, memory addressing. RISC vs CISC, how the ISA supports high-level languages, quantitative approach to ISA design. Example ISAs (e.g. MIPS, RISC-V). ISA requirements for embedded systems.
Pipelined processor design; pipeline hazards and interlocks, control prediction techniques and their usage.
Out-of-order execution; scoreboards, reservation stations, register renaming, quantitative analysis of performance.

Computer Arithmetic and ALU Design
Introduction to binary arithmetic functions; fixed-point addition, subtraction, multiplication and division.
Advanced techniques in computer arithmetic; carry-look ahead adders, parallel-prefix adders, Booth-coded multipliers, Wallace and Dadda trees, sub-word parallelism, fractional fixed-point multiply- accumulate operations.
Floating-point computations; IEEE standard, floating-point addition and multiplication, high-performance fused-multiply-add architectures.

Memory System Design
Memory hierarchies; review of principles, quantitative analysis of memory hierarchy performance; exploring the design space of cache parameters.
Cache coherence in multi-core architectures; protocols and implementation techniques.
Main memory design; Interfacing between processor and memory, synchronous and asynchronous bus protocols.
Error detection and correction schemes; parity, Hamming codes, SECDED.

This course replaced Computer Design (INFR09046) and Computer Architecture (INFR09009) from 2019/20.

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CARD: Assessed Course Assignments

flittlet — Tue, 18 Jul 2023 14:40:56 +0000

CARD: Assessed Course Assignments flittlet Tue, 18/07/2023 - 15:40

The coursework for Computer Architecture and Design is in two parts: Practical 1 (P1) and Practical 2 (P2).

P1 focusses on computer design using a Field-Programmable Gate Array (FPGA), and takes place during the first half of the course. P2 focusses on quantitative computer architecture using a software-based full-system simulator, and takes place during the second half of the course.

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CARD: Schedule

flittlet — Tue, 18 Jul 2023 14:40:51 +0000

CARD: Schedule flittlet Tue, 18/07/2023 - 15:40

Date	Lecture	Readings	Tutorials Solutions	Coursework
Date	Lecture	Readings	Tutorials Solutions	P1	P2
18-9-2023	L1 - Course Introduction
21-9-2023	L2 - Setting the Scene	H&P, sections 1.1 to 1.6
22-9-2023	L3 - Principles of Computer Architecture	H&P, sections 1.8 and 1.9		OUT
25-9-2023	L4 - Verilog (1)	See Verilog Language Reference section of the Library Resources page (ongoing reading)
28-9-2023	L5 - Boolean Logic and Gates	M&C, chapter 2
29-9-2023	L6 - Verilog (2)	See Verilog Language Reference section of the Library Resources page (ongoing reading)
2-10-2023	L7 - Logic Minimization	M&C, chapter 3	T1
5-10-2-23	L8 - Instruction Set Architecture	H&P, appendix A
6-10-2023	L9 - Pipelined Processor Design (1)	H&P, section C-1
9-10-2023	L10 - Pipelined Processor Design (2)		T2 S1
12-10-2023	L11 - Pipeline Hazards	H&P, section C-2
13-10-2023	L12 - Latches and Flip-flops	M&C, sections 5.1 to 5.4
16-10-2023	L13 - Sequential Logic	M&C, sections 5.5 to 5.8 and 8.4 to 8.6	T3 S2
19-10-2023	L14 - RTL Design	M&C, chapter 8
20-10-2023	L15 - Branch Prediction (part 1)	H&P, pp. C-22 to C-26, and C-35 to C-37			OUT
23-10-2023	L16 - Branch Prediction (part 2)	H&P, section 3.3	T4 S3
26-10-2023	L17 - Dynamic Instruction Scheduling	H&P, sections 3.4 to 3.6		IN
27-10-2023	L18 - Tomasulo's Algorithm	H&P, pp. 195 to 208, and section 3.9
30-10-2023	L19 - High-speed Addition	M&C, section 4.5; H&P-online J-37 to J-41	T5 S4
2-11-2023	L20 - Multipliers	H&P-online, sections J-50 to J-54	T5 S4
6-11-2023	L21 - Multipliers (continued)		T6
9-11-2023	L22 - Memory Hierarchies	Introductory : H&P appendix B	T6
13-11-2023	L23 - Cache Performance Enhancements (part 1)	Advanced : H&P chapter 2	T7 S6
16-11-2023	L24 - Advanced Arithmetic Functions	H&P-online, sections J-17 to J-20	T7 S6
20-11-2023	L25 - Cache Performance Enhancements (part 2)	H&P-online, sections J-17 to J-20	T8 S7, S8
23-11-2023	L26 - Main Memory and Error Correction	M&C, pp. 394 to 410	T8 S7, S8		IN

Links to the tutorial sheets and coursework handouts will be added as each item is released during the course.

Practical P1 is in four parts, all of which share the same handout date and submission deadline. You should plan to complete these four parts in succession during the weeks where P1 is active.

H&P = Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 6/e, 2019

H&P-online = Online appendices for Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 6/e, 2019

M&C = Mano and Ciletti, Digital Design, 6/e (Global Edition), 2019

** As the questions on tutorial sheet T5 are intended purely to stimulate discussion there are no sample solutions

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CARD: Resource List

flittlet — Tue, 18 Jul 2023 14:40:51 +0000

CARD: Resource List flittlet Tue, 18/07/2023 - 15:40

Computer Architecture and Design Resource List

You can access the reading list for this course by selecting the link above. In order to view some resources on the list, you must be logged in with your EASE account.

For more information on getting the most out of your courses Resource List, have a look at this video.

The list below summarizes the recommended textbooks for this course. However, you are strongly recommended to follow the link to the Library resource list here

Morris Mano, Michael D. Ciletti: Digital Design, Fourth Edition, Prentice Hall, 2007. (Sixth Edition now includes Verilog/VHDL material)
Hennessy and Patterson: Computer Architecture a Quantitative Approach, 5/e (2010) or 6/e (2019)
Hamacher/Vranesic/Zaky: Computer Organization, McGraw-Hill, 2001.
Mano/Kime: Logic and Computer Design Fundamentals, Pearson, 2008.
Patterson/Hennessy: Computer Organization and Design, Elsevier, 2005.
Null/Lobur: The Essentials of Computer Organization and Architecture, Jones and Bartlett Publishers, 2003.

Blackwell's bookstore also have a reading list for this course, from which you can purchase copies of these textbooks.

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CARD: Course Materials

flittlet — Tue, 18 Jul 2023 14:40:50 +0000

CARD: Course Materials flittlet Tue, 18/07/2023 - 15:40

Lecture Recordings

All lecture recordings should be accessed via Learn; you will need to log in using your EASE account. (Learn provides you with access to any lecture recordings available for this course. You will need to select the "lecture recording" link once, before you can access any direct links to a lecture recording.)

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CARD: Computer Architecture and Design

flittlet — Tue, 18 Jul 2023 14:40:50 +0000

CARD: Computer Architecture and Design flittlet Tue, 18/07/2023 - 15:40

Welcome to Computer Architecture and Design

This course runs in Semester 1. The first lecture is at 12:10pm on Monday 18th September in the Sydney Smith Lecture Room (Medical School, Doorway 1).

Course Delivery

There are normally three lectures per week in weeks 1-6, and then two lectures per week in weeks 7-10.

To support your work on coursework assignments there is a weekly drop-in lab in Appleton Tower 3.09, on Tuesdays of weeks 2 to 6, from 2pm to 4pm. Labs will be staffed by a team of laboratory demonstrators. You are welcome to drop in to any lab session. More details on coursework can be found on the Assessment pages.

There are also weekly tutorials, which run from week 3 to week 10. These are structured primarily as problem-solving workshops, each with its own examples sheet containing questions for you to work through in your own time and then discuss during tutorials. The aim of these tutorials is to explore the practical application of the theory covered in lectures, as well as providing an open forum for general Q&A.

All materials, including lecture slides, tutorial exercise sheets, and practical assignments, are available well in advance, and can be accessed from the Schedule Table, under Course Materials. You will need to be logged into Learn in order to access these materials.

This course uses Piazza as an information discussion and collaboration tool. If you've used it for previous courses you'll know all about it. If you're new to Piazza, it's a quick and efficient way for you to post questions and comments, or discuss course topica and get feedback from classmates, lab instructors, tutors, and the course lecturer. Rather than emailing questions to the teaching staff, I encourage you to post your questions on Piazza. If you have any problems or feedback for the developers, email team@piazza.com.

Please first select the link to Piazza from Learn. This will automatically create your account and autneticate you. After that, you should be able to access the Piazza forum for this class by selecting the link in the top right of every page on this site.

Course Philosophy

The philosophy of this course is that learning about computer architecture and computer design is particularly effective if reinforced by implementing key aspects of processor design, in real hardware when feasible, but also at higher levels of abstraction using simulated systems. Practical work is therefore a key component of this course, and represents 40% of the course assessment. The practical work starts with a warm-up exercise in logic design, after which you will be ready to design parts of a functioning microprocessor. You will be working with FPGA board (thanks to a generous donation from Xilinx) allowing you to test your designs in real hardware.

Learning Outcomes

On successful completion of this course, you should be able to:

Describe the structure and operating characteristics of a high-performance microprocessor, and explain the principles of: orthogonal instruction set design; pipeline hazards and interlocks; branch prediction (both static and dynamic); out-of-order execution.
Explain the design and operating principles of arithmetic units including: high-speed adders and multipliers; dividers; and floating-point units. And also demonstrate how selected fixed-point arithmetic functions can be implemented (in a laboratory setting).
Design and implement both combinational and synchronous digital systems using state-of-the-art FPGA design tools and hardware description languages.
Describe the structure and operating characteristics of memory systems; demonstrate the ability to evaluate quantitatively the performance of a combined processor and memory system with respect to cycles-per-instruction (CPI) and memory bandwidth requirements; describe the operating principles of error detection and correction techniques applied to memory systems, and design a SECDED solution for a given memory system.
Reason about the ways in which memory hierarchies can be configured to exploit locality in order to reduce average memory access times, and quantitatively evaluate the impact of varying cache design parameters (e.g. capacity, associativity, block size, and write policies) on performance; understand the operating principles of cache coherency protocols, and be able to compare and contrast different implementation techniques.

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