CARD: Computer Architecture and Design

Welcome to Computer Architecture and Design

This course runs in Semester 1. The first lecture is at 12:10pm on Monday 16th September. Please check your personal timetable to confirm the location, which is expected to be S.1 at 7 George Square.

Course Delivery

There are normally three lectures per week in weeks 1-6, and then two lectures per week in weeks 7-10. 

To support your work on coursework assignments there is a weekly drop-in lab in Appleton Tower 3.09, on Tuesdays and Wednesdays during weeks 2 to 6, from 2pm to 4pm. Labs will be staffed by a team of laboratory demonstrators. The reason for two lab sessions per weeks is simply that the room capacity is only 36 whereas the class size is around 70. You are welcome to drop in to one lab session (of your choosing) per week. More details on coursework can be found on the Assessment pages.

There are also weekly tutorials, which run from week 3 to week 10. These are structured primarily as problem-solving workshops, each with its own examples sheet containing questions for you to work through in your own time and then discuss during tutorials. The aim of these tutorials is to explore the practical application of the theory covered in lectures, as well as providing an open forum for general Q&A.

All materials, including lecture slides, tutorial exercise sheets, and practical assignments, are available well in advance, and can be accessed from the Schedule Table, under Course Materials. You will need to be logged into Learn in order to access these materials.

This course uses Piazza as an information discussion and collaboration tool. If you've used it for previous courses you'll know all about it. If you're new to Piazza, it's a quick and efficient way for you to post questions and comments, or discuss course topica and get feedback from classmates, lab instructors, tutors, and the course lecturer. Rather than emailing questions to the teaching staff, I encourage you to post your questions on Piazza. If you have any problems or feedback for the developers, email team@piazza.com.

Please first select the link to Piazza from Learn. This will automatically create your account and autneticate you. After that, you should be able to access the Piazza forum for this class by selecting the link in the top right of every page on this site.

Course Philosophy

The philosophy of this course is that learning about computer architecture and computer design is particularly effective if reinforced by implementing key aspects of processor design, in real hardware when feasible, but also at higher levels of abstraction using simulated systems. Practical work is therefore a key component of this course, and represents 40% of the course assessment. The practical work starts with a warm-up exercise in logic design, after which you will be ready to design parts of a functioning microprocessor. You will be working with FPGA board (thanks to a generous donation from Xilinx) allowing you to test your designs in real hardware.

Learning Outcomes

On successful completion of this course, you should be able to: 

• Describe the structure and operating characteristics of a high-performance microprocessor, and explain the principles of: orthogonal instruction set design; pipeline hazards and interlocks; branch prediction (both static and dynamic); out-of-order execution.
• Explain the design and operating principles of arithmetic units including: high-speed adders and multipliers; dividers; and floating-point units. And also demonstrate how selected fixed-point arithmetic functions can be implemented (in a laboratory setting).
• Design and implement both combinational and synchronous digital systems using state-of-the-art FPGA design tools and hardware description languages.
• Describe the structure and operating characteristics of memory systems; demonstrate the ability to evaluate quantitatively the performance of a combined processor and memory system with respect to cycles-per-instruction (CPI) and memory bandwidth requirements; describe the operating principles of error detection and correction techniques applied to memory systems, and design a SECDED solution for a given memory system.
• Reason about the ways in which memory hierarchies can be configured to exploit locality in order to reduce average memory access times, and quantitatively evaluate the impact of varying cache design parameters (e.g. capacity, associativity, block size, and write policies) on performance; understand the operating principles of cache coherency protocols, and be able to compare and contrast different implementation techniques.