CARD: Course Information

Course Outline

The aim of this course is to give you a comparatively deep understanding of computer architecture, to an intermediate level, together with a solid understanding of techniques used to design the logical building blocks from which a computer is constructed. We consider an intermediate level in computer architecture to extend up to the point where you will have a good understanding of instruction set architecture, single-issue in-order pipelined execution of instructions, superscalar out-of-order execution, and the memory hierarchies required by those processors. Within a processor, we explore the principles and practice of arithmetic and logic unit design, of the caches from which memory hierarchies are constructed, and the memory and logic gate technologies from which computers are constructed. Throughout the course, there is a strong emphasis on the Quantitative Approach to computer architecture; this informs not only the theoretical topics but also the practical assignments, which always embody some element of the quantitative approach.

The philosophy of this course is that learning about computer architecture is particularly effective if reinforced by implementing key aspects of processor design, in real hardware when feasible, but also at higher levels of abstraction using simulated systems. This approach has been used very effectively in the previous Computer Design and Computer Architecture courses, and feedback often cites the value placed on the lab exercises by students.

Outline Contents

Fundamentals
Review of logic design and implementation technologies; from simple combinational logic to state machines for sequential circuits; logic design using Verilog and introduction to FPGAs.
Register Transfer Level design principles; registers, clocks, timing budgets, setup and hold margins, clock skew, clock-domain crossing and synchronization, metastability.
Quantitative computer architecture; performance evaluation methods and metrics, principles of high-performance design.

Processor Architecture
Instruction Set Architecture (ISA) design; instruction set classes, registers, memory addressing. RISC vs CISC, how the ISA supports high-level languages, quantitative approach to ISA design. Example ISAs (e.g. MIPS, RISC-V). ISA requirements for embedded systems.
Pipelined processor design; pipeline hazards and interlocks, control prediction techniques and their usage.
Out-of-order execution; scoreboards, reservation stations, register renaming, quantitative analysis of performance.

Computer Arithmetic and ALU Design
Introduction to binary arithmetic functions; fixed-point addition, subtraction, multiplication and division.
Advanced techniques in computer arithmetic; carry-look ahead adders, parallel-prefix adders, Booth-coded multipliers, Wallace and Dadda trees, sub-word parallelism, fractional fixed-point multiply- accumulate operations.
Floating-point computations; IEEE standard, floating-point addition and multiplication, high-performance fused-multiply-add architectures.

Memory System Design
Memory hierarchies; review of principles, quantitative analysis of memory hierarchy performance; exploring the design space of cache parameters.
Cache coherence in multi-core architectures; protocols and implementation techniques.
Main memory design; Interfacing between processor and memory, synchronous and asynchronous bus protocols.
Error detection and correction schemes; parity, Hamming codes, SECDED.

This course replaced Computer Design (INFR09046) and Computer Architecture (INFR09009) from 2019/20.