INF2C-CS: Schedule

WeekDateSubjectReading*TutorialLabPracticals / Quiz
 1    18 Sep     
19 Sep

Introduction / Big Picture

P&H 1   
20 Sep     
21 SepData RepresentationP&H 3/e: 3.1-3.3, 3.6 (up to FP add) 
P&H 4/e: 2.4, 3.1,3.2, 3.5 (up to FP add) 
P&H 5/e: 2.4, 3.1,3.2, 3.5 (up to FP add) 
   
22 Sep     
 
225 Sep   
  • Lab 1: Intro to MIPS and MARS IDE
  • Source files
  • hexOut_solution.s
  • binOut_solution.s
 
26 SepData Representation 2As previous lecture   
27 Sep     
28 SepMIPS ISAP&H 3/e: 2.1-2.9, A.1-6, A.9 
P&H 4/e: 2.1-2.8, B.1-6, B.9 
P&H 5/e: 2.1-2.8, A.1-6, A.9 
   
29 Sep     
 
32 Oct  Tutorial 1
  • Lab 2: MIPS programming
  • Source file
  • memread_solution.s

Note: Make sure "Settings->Initialize program counter to global 'main' if defined" is ticked in MARS, or you will see an error.

 
3 OctMIPS ISA 2As previous lecture   
4 Oct     
5 OctMIPS ISA 3As previous lecture   
6 Oct  


Tutorial 1 Solutions

  
 
409 Oct  

Tutorial 2

Lab 3: GitHub and C programming 

Github Classroom 
Quiz 1 released
10 OctC programming language 1K&R 2/e for reference 
J. Maassen's C for Java programmers  
S. Simpson's Learning C from Java 
I. Gupta's C for Java programmers 
I. Kennedy's Top tips to help the Java programmer code in C  
  Quiz 1 DUE
11 Oct      
12 Oct      
13 Oct C programming language 2As previous lectureTutorial 2 Solutions  

coursework1.pdf

Github Classroom

 
516 Oct     
17 OctC programming language 3As previous lecture   
18 Oct      
19 Oct 


 
   
20 OctLogic Design 1P&H 3/e (on CD): B1-3 (up to ROMs), B8 (up to Verilog), B10 
P&H 4/e (on CD): C1-3 (up to ROMs), C7, C8 (up to Verilog), C10 
P&H 5/e: B1-3 (up to ROMs), B5 (up to "Tailoring to MIPS"), B7, B8 (up to Verilog), B10 
   
 
623 Oct  Tutorial 3  
24 OctLogic design 2 (starts from slide 31)As previous lecture   
25 Oct      
26 Oct 

 





 
   
27 Oct Processor design: Single-cycle processorP&H 3/e: 5.1-5.4 
P&H 4/e: 4.1-4.4 
P&H 5/e: 4.1-4.4
Tutorial 3 Solutions  Practical 1 DUE 

marking-details.pdf 
 
730 Oct  

Tutorial 4

  
31 OctProcessor design: Multi-cycle processor 1P&H 3/e: 4.2, 5.5 
P&H 4/e and 5/e: 1.4 (4/e) or 1.6 (5/e) for CPU performance 
H&P chapter on multi-cycle design 
   
1 Nov     
2 Nov     
3 Nov Processor design: Multi-cycle processor 2 As previous lecture Tutorial 4 Solutions   
 
86 Nov    Quiz 2 released
7 NovMemory hierarchy 1P&H 3/e: 7.1, 7.2 
P&H 4/e: 5.1, 5.2 
P&H 5/e: 5.1, 5.3 
  Quiz 2 DUE
8 Nov      
9 Nov      
10 Nov Memory hierarchy 2 As previous lecture  Coursework 2 

GitHub Classroom
 
913 Nov  Tutorial 5  
14 NovVirtual Memory 1P&H 3/e: 7.4 
P&H 4/e: 5.4 
P&H 5/e: 5.7  
   
15 Nov      
16 Nov      
17 Nov Virtual memory 2As previous lectureTutorial 5 Solutions   
 
1020 Nov  Tutorial 6  
21 NovExceptions & processor management1P&H 3/e: 5.6, A.7 
P&H 4/e: 4.9, B.7 
P&H 5/e: 4.9, A.7 
S&G 5/e: 2.5.1, 4.1-4.3 
S&G 8/e and 9/e: 1.6, 2.3, 3.1, 3.2 
   
22 Nov      
23 Nov 


 
   
24 Nov 

Exceptions & processor management 2 


Revision/Wrap up

 Tutorial 6 Solutions Coursework 2 DUE
 
1127 Nov     
28 NovNo lecture    
29 Nov     
30 Nov     
1 DecNo lecture    
 
5-?? DecExam prep and exam    

 

* The abbreviations used in the Reading column are:

  • P & H: D.A. Patterson and J.L. Hennessy, Computer Organisation and Design, Morgan Kaufmann, 2/e 1998, 3/e 2005, 4/e 2008, 5/e 2013
  • S & G: A. Silbershatz and P.B. Galvin, Operating Systems Concepts, 5/e, Wiley, 1998. Later editions also fine.
  • K & R: B.W. Kernighan and D.M. Ritchie The C Programming Language, 2/e, Prentice Hall PTR, 1998
License
All rights reserved The University of Edinburgh