CARD: Assessment

All coursework submissions should be made via Learn.

Good Scholarly Practice

Please remember the good scholarly practice requirements of the University regarding work for credit. You can find guidance at the School page, which also has links to the relevant University pages:

• https://web.inf.ed.ac.uk/infweb/admin/policies/academic-misconduct

Getting started

The assignments in P1 make use of an Electronic Design Automation (EDA) package from Xilinx called Vivado. The most convenient way to use Vivado is to download and install it on your laptop (Windows or Linux only; sorry there's no Mac version!). A free version of Vivado is available for download from Xilinx, which will require you to register with Xilinx. Online help and documentation from Xilinx on how to install Vivado is available here.

It is important that you install version 2021.1 of Vivado, as this is the version we use in the lab and for which the exercises have been built. This version can be selected in the Vivado download page by selecting the link to 2021.1 in the left-hand column under the Version heading. You can either install Vivado using a self-extracting web installer for your preferred O/S (~220 MB in size) or else by downloading a unified installer for all operating systems as a single file (~52 GB). Either way, you should select the full-product installation and during installation select the webpack version - this gives you a single node-locked license for personal use on your own machine.

We also have Vivado installed on DICE, so you can access it from lab machines if/when these are accessible, or you can access a DICE machine via the Informatics Remote Desktop Service from anywhere. The Vivado software allows you to create hardware designs and simulate them. It also allows you to map your design to a Field Programmable Gate Array (FPGA) and program your hardware design into an FPGA to operate it in a realistic real-time environment. The FPGA board we use in this course is the PYNQ-Z2 board (pictured above). You are each entitled to loan a PYNQ-Z2 board from the School of Informatics for the duration of the CARD course. Details on how to access these will be given during class.

Practical 1 (P1) consists of four sub-parts (a) to (d). Part (a) aims to introduce you to the Xilinx design software used to program the FPGAs. It begins with a very simple design to take you through all the stages of implementing logic in FPGAs. Along the way you will be introduced to the hardware description language, Verilog, and to the process of simulating a logic design described in Verilog. P1.(b)  and P1.(c) require you to design and implement key components of a processor. P1.(d) brings these components together in a RISC-V processor and focusses on how performance can be improved through microarchitectural enhancements (which you will design).

Practical 2 (P2) operates at a higher level, and is based on a full-system simulator. The aim is to use simulation to explore a particular aspect of the design space of a high-performance processor (or memory system) using quantitative methods.

Each practical relates to specific aspects of the course that have been covered prior to, or during the practical, and is capable of being completed within the allotted time. You are expected to organise your own time, and therefore all sub-parts of P1 are made available at the same time.

Information about using the Xilinx FPGA board is contained in the first assignment handout for P1 part (a).

Practical Weightings

Practicals P1 and P2 are equally weighted and are marked out of 50. Therefore, as the practical work contributes 40% of the overall course mark, P1 and P2 are each worth 20% of the course mark. P1 comprises four sub-parts; (a), (b), (c) and (d), which should be attempted in that order. The number of marks available for each part of P1, as well as P2, are shown in the table below. All parts of P1 have some marks awarded for a demonstration of your solution to a lab instructor. Details of how to do this are explained in the handout and marking documents for each part of P1 (also available in LEARN, under the Assessment section).

Submission and Assessment of P1

Your submission for P1 involves briefly demonstrating each part to a lab instructor, plus a written final report covering parts (b), (c) and (d). The demonstrations give you an opportunity to explain your solutions to a lab instructor. This is intended to be a light-weight activity involving a brief chat with an instructor, during which you can give a quick run-through of your work and answer some questions. A checklist for use during each demonstration is provided within the marking scheme published for each part of P1. This means that both you and the lab instructor know what is expected and what will be assessed.

Ask a lab instructor for a brief one-to-one session during one of the workshop sessions when you're ready to explain the solution to each part of P1. These workshops are in your CARD calendar and run during the first half of the course.

You need to have completed the demonstrations for P1 by the P1 submission deadline, but you can do this in stages -- as and when you complete each part, if you want to do it while it is all still fresh in your mind. The only requirement is that a lab instructor has had a chance to talk to you about each of your solutions by the P1 submission deadline. They will record a mark for your demonstration, which you will be able to see on Gradescope.

Submission and Assessment of P2

P2 involves the submission of a written report and the implementation of your solution by the submission deadline. There is no requirement to demonstrate your solution for P2.

Accessing the Assignments and Related Files

There is a marking scheme and submission checklist for each practical component, which also contains guidance on the expected contents of each report. These are available along with the assignment documents, and any related files or Zipped folders you will need, on the LEARN page for each specific assignment part. These are listed on this page, below this section.

Feedback on Assignments
Formative feedback is provided by laborary demonstrators during laboratory sessions. They are there to help you understand the task, and may give hints regarding the solution, but you are expected to define your own solutions and write your own Verilog descriptions. Quantitative feedback on your performance in the course assignments will be provided via the summative assessment of laboratory practical exercises. Marks and feedback on reports will be returned for each practical within 2 weeks of the submission deadline. Formative assessment of the lab exercises will be provided during laboratory sessions and tutorials. This will generally take the form of verbal feedback from the laboratory teaching staff on the quality of your designs and how you could improve them.