CARD: RISC-V Instruction Set References

The RISC-V instruction set architecture (ISA) and related specifications are maintained by the RISC-V consortium. The ISA is defined in two volumes. Volume 1 specifies the instruction set and programming model available to code running without privileges (i.e. ordinary User code), and is essentially the ISA targeted by compilers. Volume 2 specifies the additional elements of the instruction set and programming model that are available to code running with privileges (i.e. operating system kernel code, or hypervisor code). Links to these specifications are listed below:

  • Volume 1, unprivileged ISA specification, version 20240411 [PDF]
  • Volume 2, Privileged ISA specification, version 20240411 [PDF]

RISC-V is an open architecture, which means that there is no proprietary ownership of the ISA, which is developed in Github. Anyone is freely permitted to implement the ISA. There is an ongoing project to define what it means for an implementation to be in compliance with the ISA.

 

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