CARD: Schedule

The schedule table below shows how the course of lectures appears in the calendar, and for each lecture there is a link to the PDF of the slides from that lecture. You will need to be logged in to Learn to access the PDFs.

The Readings column gives reading references for each lecture. You should try to read around each topic, using the suggested references, in advance of each lecture if possible. 

For each week where there are tutorial workshops there is an entry in the Tutorials and Solutions column, and a link to the worksheet will go live at least a week before the tutorial is scheduled. A link to the solutions will appear the week after each tutorial.

 The coursework column shows the date on which practical P1 is available (ISSUED) and the deadline for submission of the write-up (SUBMIT). P1 is dividd into five sub-parts, all of which share the same handout date and submission deadline. You should plan to complete these five parts in succession during the weeks where P1 is active. Some recommended milestones for completion and sign-off of parts (a) to (e) of P1 are shown in the P1 column. 

DateLectureReadings

Tutorials

Solutions

Coursework
P1
15-9-2025L1 - Course Introduction   
18-9-2025L2 - Setting the SceneH&P, sections 1.1 to 1.6 
19-9-2025L3 - Principles of Computer ArchitectureH&P, sections 1.8 and 1.9ISSUED
22-9-2025L4 - Verilog (1)See Verilog Language Reference section of the Library Resources page (ongoing reading)  
25-9-2025L5 - Boolean Logic and GatesM&C, chapter 2 
26-9-2025L6 - Verilog (2)See Verilog Language Reference section of  the Library Resources page (ongoing reading) 
29-11-2025L7 - Logic MinimizationM&C, chapter 3T1 
2-10-2025L8 - Instruction Set ArchitectureH&P, appendix A(a) done
3-10-2025L9 - High-speed AdditionM&C, section 4.5; H&P-online J-37 to J-41 
6-10-2025L10 - Pipelined Processor DesignH&P, section C-1

T2

S1

 
9-10-2025L11 - Pipelined Processor Design (continued)(continue reading H&P, secotn C-1) 
10-10-2025L12 - Pipeline HazardsH&P, section C-2(b) done
13-10-2025L13 - MultipliersH&P-online, sections J-50 to J-54

T3

S2

 
16-10-2025L14 - Multipliers (continued)(continue reading sections J-50 to J-54) 
17-10-2025L15 - Latches and Flip-flopsM&C, sections 5.1 to 5.4(c) done
20-10-2025L16 - Sequential LogicM&C, sections 5.5 to 5.8 and 8.4 to 8.6

T4

S3

 
23-10-2025L17 - RTL DesignM&C, chapter 8 
24-10-2025L18 - RTL design (continued)M&C, chapter 8 
27-10-2025L19 - Advanced Arithmetic FunctionsH&P-online, sections J-17 to J-20

T5

S4

 
30-10-2025L20 - Branch Prediction (part 1)H&P, pp. C-22 to C-26, and C-35 to C-37(d) done
31-10-2025L21 - Branch Prediction (part 2)H&P, section 3.3 
3-11-2025L22 - Dynamic Instruction SchedulingH&P, sections 3.4 to 3.6T6 
6-11-2025L23 - Memory HierarchiesIntroductory : H&P appendix B 
10-11-2025L24 - Tomasulo's AlgorithmH&P, pp. 195 to 208, and section 3.9

T7

S6

 
13-11-2025L25 - Cache Performance Enhancements (part 1)Advanced : H&P chapter 2(e) done
17-11-2025L26 - Cache Performance Enhancements (part 2)H&P-online, sections J-17 to J-20

T8

S7, S8

write-up
20-11-2025L27 - Main Memory and Error CorrectionM&C, pp. 394 to 410SUBMIT

Links to the tutorial sheets and coursework handouts will be added as each item is released during the course.

H&P = Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 6/e, 2019

H&P-online = Online appendices for H& P [download]

M&C = Mano and Ciletti, Digital Design, 6/e (Global Edition), 2019

** As the questions on tutorial sheet T5 are intended purely to stimulate discussion there are no sample solutions

There is also a set of revision questions related to floating-point arithmetic, and outline solutions.

License
All rights reserved The University of Edinburgh