Date | Lecture | Readings | Tutorials Solutions | Coursework | |
---|---|---|---|---|---|
P1 | P2 | ||||
18-9-2023 | L1 - Course Introduction | ||||
21-9-2023 | L2 - Setting the Scene | H&P, sections 1.1 to 1.6 | |||
22-9-2023 | L3 - Principles of Computer Architecture | H&P, sections 1.8 and 1.9 | OUT | ||
25-9-2023 | L4 - Verilog (1) | See Verilog Language Reference section of the Library Resources page (ongoing reading) | |||
28-9-2023 | L5 - Boolean Logic and Gates | M&C, chapter 2 | |||
29-9-2023 | L6 - Verilog (2) | See Verilog Language Reference section of the Library Resources page (ongoing reading) | |||
2-10-2023 | L7 - Logic Minimization | M&C, chapter 3 | T1 | ||
5-10-2-23 | L8 - Instruction Set Architecture | H&P, appendix A | |||
6-10-2023 | L9 - Pipelined Processor Design (1) | H&P, section C-1 | |||
9-10-2023 | L10 - Pipelined Processor Design (2) | ||||
12-10-2023 | L11 - Pipeline Hazards | H&P, section C-2 | |||
13-10-2023 | L12 - Latches and Flip-flops | M&C, sections 5.1 to 5.4 | |||
16-10-2023 | L13 - Sequential Logic | M&C, sections 5.5 to 5.8 and 8.4 to 8.6 | |||
19-10-2023 | L14 - RTL Design | M&C, chapter 8 | |||
20-10-2023 | L15 - Branch Prediction (part 1) | H&P, pp. C-22 to C-26, and C-35 to C-37 | OUT | ||
23-10-2023 | L16 - Branch Prediction (part 2) | H&P, section 3.3 | |||
26-10-2023 | L17 - Dynamic Instruction Scheduling | H&P, sections 3.4 to 3.6 | IN | ||
27-10-2023 | L18 - Tomasulo's Algorithm | H&P, pp. 195 to 208, and section 3.9 | |||
30-10-2023 | L19 - High-speed Addition | M&C, section 4.5; H&P-online J-37 to J-41 | |||
2-11-2023 | L20 - Multipliers | H&P-online, sections J-50 to J-54 | |||
6-11-2023 | L21 - Multipliers (continued) | T6 | |||
9-11-2023 | L22 - Memory Hierarchies | Introductory : H&P appendix B | |||
13-11-2023 | L23 - Cache Performance Enhancements (part 1) | Advanced : H&P chapter 2 | |||
16-11-2023 | L24 - Advanced Arithmetic Functions | H&P-online, sections J-17 to J-20 | |||
20-11-2023 | L25 - Cache Performance Enhancements (part 2) | H&P-online, sections J-17 to J-20 | |||
23-11-2023 | L26 - Main Memory and Error Correction | M&C, pp. 394 to 410 | IN |
Links to the tutorial sheets and coursework handouts will be added as each item is released during the course.
Practical P1 is in four parts, all of which share the same handout date and submission deadline. You should plan to complete these four parts in succession during the weeks where P1 is active.
H&P = Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 6/e, 2019
H&P-online = Online appendices for Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 6/e, 2019
M&C = Mano and Ciletti, Digital Design, 6/e (Global Edition), 2019
** As the questions on tutorial sheet T5 are intended purely to stimulate discussion there are no sample solutions