CARD: Schedule

The schedule table below shows how the course of lectures appears in the calendar, and for each lecture there is a link to the PDF of the slides from that lecture. You will need to be logged in to Learn to access the PDFs.

The Readings column gives reading references for each lecture. You should try to read around each topic, using the suggested references, in advance of each lecture if possible. 

For each week where there are tutorial workshops there is an entry in the Tutorials and Solutions column, and a link to the worksheet will go live at least a week before the tutorial is scheduled. A link to the solutions will appear the week after each tutorial.

 The coursework column shows the date on which practical P1 is available (ISSUED) and the deadline for submission of the write-up (SUBMIT). P1 is divided into five sub-parts, all of which share the same handout date and submission deadline. You should plan to complete these five parts in succession during the weeks where P1 is active. Some recommended milestones for completion and sign-off of parts (a) to (e) of P1 are shown in the P1 column. 

DateLectureReadings

Tutorials

Solutions

Coursework
P1
21/09/2026L1 - Course Introduction   
24/09/2026L2 - Setting the SceneH&P, sections 1.1 to 1.6 
25/09/2026L3 - Principles of Computer ArchitectureH&P, sections 1.8 and 1.9ISSUED
28/09/2026L4 - Verilog (part 1)See Verilog Language Reference section of the Library Resources page (ongoing reading)  
01/10/2026L5 - Boolean Logic and GatesM&C, chapter 2 
02/10/2026L6 - Verilog (part 2)See Verilog Language Reference section of  the Library Resources page (ongoing reading) 
05/10/2026L7 - Logic MinimizationM&C, chapter 3T1 
08/10/2026L8 - High-speed AdditionM&C, section 4.5; H&P-online J-37 to J-41(a) done
09/10/2026L9 - MultipliersH&P-online, sections J-50 to J-54 
12/10/2026L10 - Instruction Set ArchitectureH&P, appendix A

T2

S1

 
15/10/2026L11 - Pipelined Processor Design (part 1)H&P, section C-1 
16/10/2026L12 - Pipelined Processor Design (part 2) (b) done
19/10/2026L13 - Pipeline HazardsH&P, section C-2

T3

S2

 
22/10/2026L14 - Sequential LogicM&C, sections 5.1 to 5.8 and 8.4 to 8.6 
23/10/2026L15 - RTL Design (part 1)M&C, chapter 8(c) done
26/10/2026L16 - RTL design (part 2)M&C, chapter 8

T4

S3

 
29/10/2026L17 - Advanced Arithmetic FunctionsH&P-online, sections J-17 to J-20 
30/10/2026L18 - Branch Prediction (part 1)H&P, pp. C-22 to C-26, and C-35 to C-37 
02/11/2026L19 - Branch Prediction (part 2)H&P, section 3.3

T5

S4

 
05/11/2026L20 - Memory HierarchiesIntroductory : H&P appendix B(d) done
06/11/2026L21 - Cache Performance Enhancements (part 1)Advanced : H&P chapter 2 
09/11/2026L22 - Cache Performance Enhancements (part 2)H&P-online, sections J-17 to J-20

T6

S5

 
12/11/2026L23 - Main Memory and Error CorrectionM&C, pp. 394 to 410 
16/11/2026L24 - Dynamic Instruction SchedulingH&P, sections 3.4 to 3.6

T7

S6

 
19/11/2026L25 - Tomasulo's AlgorithmH&P, pp. 195 to 208, and section 3.9(e) done
23/11/2026L26 - Optimizing PerformanceH&P, pp. 347 to 357

T8

S8

write-up
26/11/2026L27 - Set aside for revision lecture Please post questions in advanceSUBMIT

Links to the tutorial sheets and coursework handouts will be added as each item is released during the course.

H&P = Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 6/e, 2019

H&P-online = Online appendices for H& P [download]

M&C = Mano and Ciletti, Digital Design, 6/e (Global Edition), 2019

** As the questions on tutorial sheet T7 are intended purely to stimulate discussion there are no sample solutions

There is also a set of revision questions related to floating-point arithmetic, and outline solutions.

License
All rights reserved The University of Edinburgh