CARD: Schedule

The schedule table below shows how the course of lectures appears in the calendar, and for each lecture there is a link to the PDF of the slides from that lecture. You will need to be logged in to Learn to access the PDFs.

The Readings column gives reading references for each lecture. You should try to read around each topic, using the suggested references, in advance of each lecture if possible. For each week where there are tutorial workshops there is an entry in the Tutorials and Solutions column, and a link to the worksheet will go live at least a week before the tutorial is scheduled. A link to the solutions will appear the week after each tutorial. The coursework columns show the date on which practicals P1 and P2 go out, and the deadline for submission of the write-up for each one. 

DateLectureReadings

Tutorials

Solutions

Coursework
P1P2
16-9-2024L1 - Course Introduction    
19-9-2024L2 - Setting the SceneH&P, sections 1.1 to 1.6  
20-9-2024L3 - Principles of Computer ArchitectureH&P, sections 1.8 and 1.9OUT 
23-9-2024L4 - Verilog (1)See Verilog Language Reference section of the Library Resources page (ongoing reading)   
26-9-2024L5 - Boolean Logic and GatesM&C, chapter 2  
27-9-2024L6 - Verilog (2)See Verilog Language Reference section of  the Library Resources page (ongoing reading)  
30-11-2024L7 - Logic MinimizationM&C, chapter 3T1  
3-10-2-24L8 - Instruction Set ArchitectureH&P, appendix A  
4-10-2024L9 - Pipelined Processor DesignH&P, section C-1  
7-10-2024L10 - Pipelined Processor Design (continued) 

T2

S1

  
10-10-2024L11 - Pipeline HazardsH&P, section C-2  
11-10-2024L12 - Latches and Flip-flopsM&C, sections 5.1 to 5.4  
14-10-2024L13 - Sequential LogicM&C, sections 5.5 to 5.8 and 8.4 to 8.6

T3

S2

  
17-10-2024L14 - RTL DesignM&C, chapter 8  
18-10-2024L14 - RTL design (continued) M&C, chapter 8 OUT
21-10-2024L15 - Branch Prediction (part 1)H&P, pp. C-22 to C-26, and C-35 to C-37

T4

S3

  
24-10-2024L16 - Branch Prediction (part 2)H&P, section 3.3IN 
25-10-2024L17 - Dynamic Instruction SchedulingH&P, sections 3.4 to 3.6  
28-10-2024

L18 - Tomasulo's Algorithm

Slides 44-48 updated (8 Dec)

Slides 22-28 updated (14-Dec)

H&P, pp. 195 to 208, and section 3.9

T5

S4

  
31-10-2024L19 - High-speed Addition M&C, section 4.5; H&P-online J-37 to J-41  
1-11-2024

L20 - Multipliers

Slide 19 updated (15-Dec)

H&P-online, sections J-50 to J-54  
4-11-2024L21 - Multipliers (continued) T6  
7-11-2024L22 - Memory HierarchiesIntroductory : H&P appendix B  
11-11-2024L23 - Cache Performance Enhancements (part 1)Advanced : H&P chapter 2

T7

S6

  
14-11-2024L24 - Advanced Arithmetic FunctionsH&P-online, sections J-17 to J-20  
18-11-2024L25 - Cache Performance Enhancements (part 2)H&P-online, sections J-17 to J-20

T8

S7, S8

  
21-11-2024L26 - Main Memory and Error CorrectionM&C, pp. 394 to 410 IN

Links to the tutorial sheets and coursework handouts will be added as each item is released during the course.

Practical P1 is in four parts, all of which share the same handout date and submission deadline. You should plan to complete these four parts in succession during the weeks where P1 is active. 

H&P = Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 6/e, 2019

H&P-online = Online appendices for Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 6/e, 2019

M&C = Mano and Ciletti, Digital Design, 6/e (Global Edition), 2019

** As the questions on tutorial sheet T5 are intended purely to stimulate discussion there are no sample solutions

There is also a set of revision questions related to floating-point arithmetic, and outline solutions.

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