CARD: Verilog
- You can use free Icarus Verilog simulator and see the results using gtkwave (already installed on DICE machines)
- Verilog Quick Reference Guide
- Verilog Tutorial
- Blocking versus Non-blocking Assignments in Verilog (highly recommended reading)
- State Machine Coding Styles (recommended reading)
- Highly recommended paper on X values in Verilog (I'm still in love with my X)
- Another highly recommended paper on Verilog coding styles that can lead to mismatches between simulation results and synthesis results (RTL Coding Styles That Yield Simulation and Synthesis Mismatches). In particular, section 4.3 explains why casex should not be used (except in a testbench, where it may still be useful).
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